mirror of
https://github.com/Atmosphere-NX/Atmosphere.git
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365 lines
15 KiB
C++
365 lines
15 KiB
C++
/*
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* Copyright (c) 2018-2020 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <exosphere.hpp>
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#include "../secmon_cache.hpp"
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#include "../secmon_cpu_context.hpp"
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#include "../secmon_error.hpp"
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#include "secmon_smc_power_management.hpp"
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#include "secmon_smc_se_lock.hpp"
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#include "sc7fw_bin.h"
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namespace ams::secmon {
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/* Declare assembly functionality. */
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void *GetCoreExceptionStackVirtual();
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}
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namespace ams::secmon::smc {
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/* Declare assembly power-management functionality. */
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void PivotStackAndInvoke(void *stack, void (*function)());
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void FinalizePowerOff();
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namespace {
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constexpr inline const uintptr_t PMC = MemoryRegionVirtualDevicePmc.GetAddress();
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constexpr inline const uintptr_t APB_MISC = MemoryRegionVirtualDeviceApbMisc.GetAddress();
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constexpr inline const uintptr_t GPIO = MemoryRegionVirtualDeviceGpio.GetAddress();
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constexpr inline const uintptr_t CLK_RST = MemoryRegionVirtualDeviceClkRst.GetAddress();
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constexpr inline const uintptr_t EVP = secmon::MemoryRegionVirtualDeviceExceptionVectors.GetAddress();
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constexpr inline const uintptr_t FLOW_CTLR = MemoryRegionVirtualDeviceFlowController.GetAddress();
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constexpr inline uintptr_t CommonSmcStackTop = MemoryRegionVirtualTzramVolatileData.GetEndAddress() - (0x80 * (NumCores - 1));
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enum PowerStateType {
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PowerStateType_StandBy = 0,
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PowerStateType_PowerDown = 1,
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};
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enum PowerStateId {
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PowerStateId_Sc7 = 27,
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};
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/* http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf Page 46 */
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struct SuspendCpuPowerState {
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using StateId = util::BitPack32::Field< 0, 16, PowerStateId>;
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using StateType = util::BitPack32::Field<16, 1, PowerStateType>;
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using PowerLevel = util::BitPack32::Field<24, 2, u32>;
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};
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constinit bool g_charger_hi_z_mode_enabled = false;
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constinit const reg::BitsMask CpuPowerGateStatusMasks[NumCores] = {
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PMC_REG_BITS_MASK(PWRGATE_STATUS_CE0),
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PMC_REG_BITS_MASK(PWRGATE_STATUS_CE1),
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PMC_REG_BITS_MASK(PWRGATE_STATUS_CE2),
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PMC_REG_BITS_MASK(PWRGATE_STATUS_CE3),
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};
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constinit const APBDEV_PMC_PWRGATE_TOGGLE_PARTID CpuPowerGateTogglePartitionIds[NumCores] = {
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APBDEV_PMC_PWRGATE_TOGGLE_PARTID_CE0,
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APBDEV_PMC_PWRGATE_TOGGLE_PARTID_CE1,
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APBDEV_PMC_PWRGATE_TOGGLE_PARTID_CE2,
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APBDEV_PMC_PWRGATE_TOGGLE_PARTID_CE3,
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};
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bool IsCpuPoweredOn(const reg::BitsMask mask) {
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return reg::HasValue(PMC + APBDEV_PMC_PWRGATE_STATUS, REG_BITS_VALUE_FROM_MASK(mask, APBDEV_PMC_PWRGATE_STATUS_STATUS_ON));
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}
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void PowerOnCpu(const reg::BitsMask mask, u32 toggle_partid) {
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/* If the cpu is already on, we have nothing to do. */
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if (IsCpuPoweredOn(mask)) {
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return;
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}
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/* Wait until nothing is being powergated. */
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int timeout = 5000;
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while (true) {
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if (reg::HasValue(PMC + APBDEV_PMC_PWRGATE_TOGGLE, PMC_REG_BITS_ENUM(PWRGATE_TOGGLE_START, DISABLE))) {
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break;
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}
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util::WaitMicroSeconds(1);
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if ((--timeout) < 0) {
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/* NOTE: Nintendo doesn't do any error handling here... */
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return;
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}
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}
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/* Toggle on the cpu partition. */
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reg::Write(PMC + APBDEV_PMC_PWRGATE_TOGGLE, PMC_REG_BITS_ENUM (PWRGATE_TOGGLE_START, ENABLE),
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PMC_REG_BITS_VALUE(PWRGATE_TOGGLE_PARTID, toggle_partid));
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/* Wait up to 5000 us for the powergate to complete. */
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timeout = 5000;
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while (true) {
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if (IsCpuPoweredOn(mask)) {
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break;
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}
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util::WaitMicroSeconds(1);
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if ((--timeout) < 0) {
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/* NOTE: Nintendo doesn't do any error handling here... */
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return;
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}
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}
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}
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void ResetCpu(int which_core) {
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reg::Write(CLK_RST + CLK_RST_CONTROLLER_RST_CPUG_CMPLX_SET, REG_BITS_VALUE(which_core + 0x00, 1, 1), /* CPURESETn */
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REG_BITS_VALUE(which_core + 0x10, 1, 1)); /* CORERESETn */
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}
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void StartCpu(int which_core) {
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reg::Write(CLK_RST + CLK_RST_CONTROLLER_RST_CPUG_CMPLX_CLR, REG_BITS_VALUE(which_core + 0x00, 1, 1), /* CPURESETn */
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REG_BITS_VALUE(which_core + 0x10, 1, 1)); /* CORERESETn */
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}
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void PowerOffCpu() {
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/* Get the current core id. */
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const auto core_id = hw::GetCurrentCoreId();
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/* Configure the flow controller to prepare for shutting down the current core. */
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flow::SetCpuCsr(core_id, FLOW_CTLR_CPUN_CSR_ENABLE_EXT_POWERGATE_CPU_ONLY);
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flow::SetHaltCpuEvents(core_id, false);
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flow::SetCc4Ctrl(core_id, 0);
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/* Save the core's context for restoration on next power-on. */
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SaveDebugRegisters();
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SetCoreOff();
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/* Ensure there are no pending memory transactions prior to our power-down. */
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FlushEntireDataCache();
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/* Finalize our powerdown and wait for an interrupt. */
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FinalizePowerOff();
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}
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void ValidateSocStateForSuspend() {
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/* TODO */
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}
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void SaveSecureContextForErista() {
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/* TODO */
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}
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void SaveSecureContextForMariko() {
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/* TODO */
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}
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void SaveSecureContext() {
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const auto soc_type = GetSocType();
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if (soc_type == fuse::SocType_Erista) {
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SaveSecureContextForErista();
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} else /* if (soc_type == fuse::SocType_Mariko) */ {
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SaveSecureContextForMariko();
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}
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}
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void LoadAndStartSc7BpmpFirmware() {
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/* Set the PMC as insecure, so that the BPMP firmware can access it. */
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reg::ReadWrite(APB_MISC + APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG0_0, SLAVE_SECURITY_REG_BITS_ENUM(0, PMC, DISABLE));
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/* Set the exception vectors for the bpmp. RESET should point to RESET, all others should point to generic exception/panic. */
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constexpr const u32 Sc7FirmwareResetVector = static_cast<u32>(MemoryRegionPhysicalIramSc7Firmware.GetAddress() + 0x0);
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constexpr const u32 Sc7FirmwarePanicVector = static_cast<u32>(MemoryRegionPhysicalIramSc7Firmware.GetAddress() + 0x4);
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reg::Write(EVP + EVP_COP_RESET_VECTOR, Sc7FirmwareResetVector);
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reg::Write(EVP + EVP_COP_UNDEF_VECTOR, Sc7FirmwarePanicVector);
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reg::Write(EVP + EVP_COP_SWI_VECTOR, Sc7FirmwarePanicVector);
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reg::Write(EVP + EVP_COP_PREFETCH_ABORT_VECTOR, Sc7FirmwarePanicVector);
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reg::Write(EVP + EVP_COP_DATA_ABORT_VECTOR, Sc7FirmwarePanicVector);
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reg::Write(EVP + EVP_COP_RSVD_VECTOR, Sc7FirmwarePanicVector);
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reg::Write(EVP + EVP_COP_IRQ_VECTOR, Sc7FirmwarePanicVector);
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reg::Write(EVP + EVP_COP_FIQ_VECTOR, Sc7FirmwarePanicVector);
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/* Disable activity monitor bpmp monitoring, so that we don't panic upon bpmp wake. */
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actmon::StopMonitoringBpmp();
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/* Load the bpmp firmware. */
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void * const sc7fw_load_address = MemoryRegionVirtualIramSc7Firmware.GetPointer<void>();
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std::memcpy(sc7fw_load_address, sc7fw_bin, sc7fw_bin_size);
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hw::FlushDataCache(sc7fw_load_address, sc7fw_bin_size);
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hw::DataSynchronizationBarrierInnerShareable();
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/* Ensure that the bpmp firmware was loaded. */
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AMS_ABORT_UNLESS(crypto::IsSameBytes(sc7fw_load_address, sc7fw_bin, sc7fw_bin_size));
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/* Clear BPMP reset. */
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reg::Write(CLK_RST + CLK_RST_CONTROLLER_RST_DEV_L_CLR, CLK_RST_REG_BITS_ENUM(RST_DEV_L_CLR_CLR_COP_RST, ENABLE));
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/* Start the bpmp. */
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reg::Write(FLOW_CTLR + FLOW_CTLR_HALT_COP_EVENTS, FLOW_REG_BITS_ENUM(HALT_COP_EVENTS_MODE, FLOW_MODE_NONE));
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}
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void SaveSecureContextAndSuspend() {
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/* Ensure there are no pending memory transactions before we continue */
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FlushEntireDataCache();
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hw::DataSynchronizationBarrierInnerShareable();
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/* Save all secure context (security engine state + tzram). */
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SaveSecureContext();
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/* Load and start the sc7 firmware on the bpmp. */
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LoadAndStartSc7BpmpFirmware();
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/* Log our suspension. */
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/* NOTE: Nintendo only does this on dev, but we will always do it. */
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if (true /* !pkg1::IsProduction() */) {
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log::SendText("OYASUMI\n", 8);
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}
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/* Finalize our powerdown and wait for an interrupt. */
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FinalizePowerOff();
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}
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SmcResult SuspendCpuImpl(SmcArguments &args) {
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/* Decode arguments. */
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const util::BitPack32 power_state = { static_cast<u32>(args.r[1]) };
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const uintptr_t entry_point = args.r[2];
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const uintptr_t context_id = args.r[3];
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const auto state_type = power_state.Get<SuspendCpuPowerState::StateType>();
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const auto state_id = power_state.Get<SuspendCpuPowerState::StateId>();
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const auto core_id = hw::GetCurrentCoreId();
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/* Validate arguments. */
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SMC_R_UNLESS(state_type == PowerStateType_PowerDown, PsciDenied);
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SMC_R_UNLESS(state_id == PowerStateId_Sc7, PsciDenied);
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/* Orchestrate charger transition to Hi-Z mode if needed. */
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if (IsChargerHiZModeEnabled()) {
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/* Ensure we can do comms over i2c-1. */
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clkrst::EnableI2c1Clock();
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/* If the charger isn't in hi-z mode, perform a transition. */
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if (!charger::IsHiZMode()) {
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charger::EnterHiZMode();
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/* Wait up to 50ms for the transition to complete. */
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const auto start_time = util::GetMicroSeconds();
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auto current_time = start_time;
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while ((current_time - start_time) <= 50'000) {
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if (auto intr_status = reg::Read(GPIO + 0x634); (intr_status & 1) == 0) {
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/* Wait 256 us to ensure the transition completes. */
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util::WaitMicroSeconds(256);
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break;
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}
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current_time = util::GetMicroSeconds();
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}
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}
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/* Disable i2c-1, since we're done communicating over it. */
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clkrst::DisableI2c1Clock();
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}
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/* Enable wake event detection. */
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pmc::EnableWakeEventDetection();
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/* Ensure that i2c-5 is usable for communicating with the pmic. */
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clkrst::EnableI2c5Clock();
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i2c::Initialize(i2c::Port_5);
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/* Orchestrate sleep entry with the pmic. */
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pmic::EnableSleep();
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/* Ensure that the soc is in a state valid for us to suspend. */
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ValidateSocStateForSuspend();
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/* Configure the pmc for sc7 entry. */
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pmc::ConfigureForSc7Entry();
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/* Configure the flow controller for sc7 entry. */
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flow::SetCc4Ctrl(core_id, 0);
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flow::SetHaltCpuEvents(core_id, false);
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flow::ClearL2FlushControl();
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flow::SetCpuCsr(core_id, FLOW_CTLR_CPUN_CSR_ENABLE_EXT_POWERGATE_CPU_TURNOFF_CPURAIL);
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/* Save the entry context. */
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SetEntryContext(core_id, entry_point, context_id);
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/* Configure the cpu context for reset. */
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SaveDebugRegisters();
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SetCoreOff();
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SetResetExpected(true);
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/* Switch to use the common smc stack (all other cores are off), and perform suspension. */
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PivotStackAndInvoke(reinterpret_cast<void *>(CommonSmcStackTop), SaveSecureContextAndSuspend);
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/* This code will never be reached. */
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__builtin_unreachable();
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}
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}
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SmcResult SmcPowerOffCpu(SmcArguments &args) {
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/* Get the current core id. */
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const auto core_id = hw::GetCurrentCoreId();
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/* Note that we're expecting a reset for the current core. */
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SetResetExpected(true);
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/* If we're on the final core, shut down directly. Otherwise, invoke with special stack. */
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if (core_id == NumCores - 1) {
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PowerOffCpu();
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} else {
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PivotStackAndInvoke(GetCoreExceptionStackVirtual(), PowerOffCpu);
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}
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/* This code will never be reached. */
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__builtin_unreachable();
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}
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SmcResult SmcPowerOnCpu(SmcArguments &args) {
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/* Get and validate the core to power on. */
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const int which_core = args.r[1];
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SMC_R_UNLESS(0 <= which_core && which_core < NumCores, PsciInvalidParameters);
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/* Ensure the core isn't already on. */
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SMC_R_UNLESS(!IsCoreOn(which_core), PsciAlreadyOn);
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/* Save the entry context. */
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SetEntryContext(which_core, args.r[2], args.r[3]);
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/* Reset the cpu. */
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ResetCpu(which_core);
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/* Turn on the core. */
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PowerOnCpu(CpuPowerGateStatusMasks[which_core], CpuPowerGateTogglePartitionIds[which_core]);
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/* Start the core. */
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StartCpu(which_core);
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return SmcResult::PsciSuccess;
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}
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SmcResult SmcSuspendCpu(SmcArguments &args) {
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return LockSecurityEngineAndInvoke(args, SuspendCpuImpl);
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}
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bool IsChargerHiZModeEnabled() {
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return g_charger_hi_z_mode_enabled;
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}
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void SetChargerHiZModeEnabled(bool en) {
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g_charger_hi_z_mode_enabled = en;
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}
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}
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