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fusee: move dsi register write to the proper configuration list

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hexkyz 2020-11-30 19:19:43 +00:00 committed by Michael Scire
parent 83fa9983bf
commit d083384f2f
6 changed files with 21 additions and 21 deletions
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8
fusee/fusee-primary/fusee-primary-main/src/di.c
View file

@ -120,9 +120,9 @@ void display_init_erista(void) {
do_register_writes(DI_BASE, display_config_dc_01, 94); do_register_writes(DI_BASE, display_config_dc_01, 94);
do_register_writes(DSI_BASE, display_config_dsi_01_init_01, 8); do_register_writes(DSI_BASE, display_config_dsi_01_init_01, 8);
do_register_writes(DSI_BASE, display_config_dsi_01_init_02_erista, 1); do_register_writes(DSI_BASE, display_config_dsi_01_init_02_erista, 1);
do_register_writes(DSI_BASE, display_config_dsi_01_init_03, 13); do_register_writes(DSI_BASE, display_config_dsi_01_init_03, 14);
do_register_writes(DSI_BASE, display_config_dsi_01_init_04_erista, 0); do_register_writes(DSI_BASE, display_config_dsi_01_init_04_erista, 0);
do_register_writes(DSI_BASE, display_config_dsi_01_init_05, 11); do_register_writes(DSI_BASE, display_config_dsi_01_init_05, 10);
do_register_writes(DSI_BASE, display_config_dsi_phy_timing_erista, 1); do_register_writes(DSI_BASE, display_config_dsi_phy_timing_erista, 1);
do_register_writes(DSI_BASE, display_config_dsi_01_init_06, 12); do_register_writes(DSI_BASE, display_config_dsi_01_init_06, 12);
do_register_writes(DSI_BASE, display_config_dsi_phy_timing_erista, 1); do_register_writes(DSI_BASE, display_config_dsi_phy_timing_erista, 1);
@ -276,9 +276,9 @@ void display_init_mariko(void) {
do_register_writes(DI_BASE, display_config_dc_01, 94); do_register_writes(DI_BASE, display_config_dc_01, 94);
do_register_writes(DSI_BASE, display_config_dsi_01_init_01, 8); do_register_writes(DSI_BASE, display_config_dsi_01_init_01, 8);
do_register_writes(DSI_BASE, display_config_dsi_01_init_02_mariko, 1); do_register_writes(DSI_BASE, display_config_dsi_01_init_02_mariko, 1);
do_register_writes(DSI_BASE, display_config_dsi_01_init_03, 13); do_register_writes(DSI_BASE, display_config_dsi_01_init_03, 14);
do_register_writes(DSI_BASE, display_config_dsi_01_init_04_mariko, 7); do_register_writes(DSI_BASE, display_config_dsi_01_init_04_mariko, 7);
do_register_writes(DSI_BASE, display_config_dsi_01_init_05, 11); do_register_writes(DSI_BASE, display_config_dsi_01_init_05, 10);
do_register_writes(DSI_BASE, display_config_dsi_phy_timing_mariko, 1); do_register_writes(DSI_BASE, display_config_dsi_phy_timing_mariko, 1);
do_register_writes(DSI_BASE, display_config_dsi_01_init_06, 12); do_register_writes(DSI_BASE, display_config_dsi_01_init_06, 12);
do_register_writes(DSI_BASE, display_config_dsi_phy_timing_mariko, 1); do_register_writes(DSI_BASE, display_config_dsi_phy_timing_mariko, 1);

6
fusee/fusee-primary/fusee-primary-main/src/di.inl
View file

@ -159,7 +159,7 @@ static const register_write_t display_config_dsi_01_init_02_mariko[1] = {
{sizeof(uint32_t) * DSI_INIT_SEQ_DATA_15_MARIKO, 0x0}, {sizeof(uint32_t) * DSI_INIT_SEQ_DATA_15_MARIKO, 0x0},
}; };
static const register_write_t display_config_dsi_01_init_03[13] = { static const register_write_t display_config_dsi_01_init_03[14] = {
{sizeof(uint32_t) * DSI_DCS_CMDS, 0}, {sizeof(uint32_t) * DSI_DCS_CMDS, 0},
{sizeof(uint32_t) * DSI_PKT_SEQ_0_LO, 0}, {sizeof(uint32_t) * DSI_PKT_SEQ_0_LO, 0},
{sizeof(uint32_t) * DSI_PKT_SEQ_1_LO, 0}, {sizeof(uint32_t) * DSI_PKT_SEQ_1_LO, 0},
@ -173,6 +173,7 @@ static const register_write_t display_config_dsi_01_init_03[13] = {
{sizeof(uint32_t) * DSI_PKT_SEQ_3_HI, 0}, {sizeof(uint32_t) * DSI_PKT_SEQ_3_HI, 0},
{sizeof(uint32_t) * DSI_PKT_SEQ_4_HI, 0}, {sizeof(uint32_t) * DSI_PKT_SEQ_4_HI, 0},
{sizeof(uint32_t) * DSI_PKT_SEQ_5_HI, 0}, {sizeof(uint32_t) * DSI_PKT_SEQ_5_HI, 0},
{sizeof(uint32_t) * DSI_CONTROL, 0},
}; };
static const register_write_t display_config_dsi_01_init_04_erista[0] = { static const register_write_t display_config_dsi_01_init_04_erista[0] = {
@ -189,8 +190,7 @@ static const register_write_t display_config_dsi_01_init_04_mariko[7] = {
{sizeof(uint32_t) * DSI_PAD_CONTROL_7_MARIKO, 0}, {sizeof(uint32_t) * DSI_PAD_CONTROL_7_MARIKO, 0},
}; };
static const register_write_t display_config_dsi_01_init_05[11] = { static const register_write_t display_config_dsi_01_init_05[10] = {
{sizeof(uint32_t) * DSI_CONTROL, 0},
{sizeof(uint32_t) * DSI_PAD_CONTROL_CD, 0}, {sizeof(uint32_t) * DSI_PAD_CONTROL_CD, 0},
{sizeof(uint32_t) * DSI_SOL_DELAY, 0x18}, {sizeof(uint32_t) * DSI_SOL_DELAY, 0x18},
{sizeof(uint32_t) * DSI_MAX_THRESHOLD, 0x1E0}, {sizeof(uint32_t) * DSI_MAX_THRESHOLD, 0x1E0},

8
fusee/fusee-secondary/src/di.c
View file

@ -120,9 +120,9 @@ void display_init_erista(void) {
do_register_writes(DI_BASE, display_config_dc_01, 94); do_register_writes(DI_BASE, display_config_dc_01, 94);
do_register_writes(DSI_BASE, display_config_dsi_01_init_01, 8); do_register_writes(DSI_BASE, display_config_dsi_01_init_01, 8);
do_register_writes(DSI_BASE, display_config_dsi_01_init_02_erista, 1); do_register_writes(DSI_BASE, display_config_dsi_01_init_02_erista, 1);
do_register_writes(DSI_BASE, display_config_dsi_01_init_03, 13); do_register_writes(DSI_BASE, display_config_dsi_01_init_03, 14);
do_register_writes(DSI_BASE, display_config_dsi_01_init_04_erista, 0); do_register_writes(DSI_BASE, display_config_dsi_01_init_04_erista, 0);
do_register_writes(DSI_BASE, display_config_dsi_01_init_05, 11); do_register_writes(DSI_BASE, display_config_dsi_01_init_05, 10);
do_register_writes(DSI_BASE, display_config_dsi_phy_timing_erista, 1); do_register_writes(DSI_BASE, display_config_dsi_phy_timing_erista, 1);
do_register_writes(DSI_BASE, display_config_dsi_01_init_06, 12); do_register_writes(DSI_BASE, display_config_dsi_01_init_06, 12);
do_register_writes(DSI_BASE, display_config_dsi_phy_timing_erista, 1); do_register_writes(DSI_BASE, display_config_dsi_phy_timing_erista, 1);
@ -276,9 +276,9 @@ void display_init_mariko(void) {
do_register_writes(DI_BASE, display_config_dc_01, 94); do_register_writes(DI_BASE, display_config_dc_01, 94);
do_register_writes(DSI_BASE, display_config_dsi_01_init_01, 8); do_register_writes(DSI_BASE, display_config_dsi_01_init_01, 8);
do_register_writes(DSI_BASE, display_config_dsi_01_init_02_mariko, 1); do_register_writes(DSI_BASE, display_config_dsi_01_init_02_mariko, 1);
do_register_writes(DSI_BASE, display_config_dsi_01_init_03, 13); do_register_writes(DSI_BASE, display_config_dsi_01_init_03, 14);
do_register_writes(DSI_BASE, display_config_dsi_01_init_04_mariko, 7); do_register_writes(DSI_BASE, display_config_dsi_01_init_04_mariko, 7);
do_register_writes(DSI_BASE, display_config_dsi_01_init_05, 11); do_register_writes(DSI_BASE, display_config_dsi_01_init_05, 10);
do_register_writes(DSI_BASE, display_config_dsi_phy_timing_mariko, 1); do_register_writes(DSI_BASE, display_config_dsi_phy_timing_mariko, 1);
do_register_writes(DSI_BASE, display_config_dsi_01_init_06, 12); do_register_writes(DSI_BASE, display_config_dsi_01_init_06, 12);
do_register_writes(DSI_BASE, display_config_dsi_phy_timing_mariko, 1); do_register_writes(DSI_BASE, display_config_dsi_phy_timing_mariko, 1);

6
fusee/fusee-secondary/src/di.inl
View file

@ -159,7 +159,7 @@ static const register_write_t display_config_dsi_01_init_02_mariko[1] = {
{sizeof(uint32_t) * DSI_INIT_SEQ_DATA_15_MARIKO, 0x0}, {sizeof(uint32_t) * DSI_INIT_SEQ_DATA_15_MARIKO, 0x0},
}; };
static const register_write_t display_config_dsi_01_init_03[13] = { static const register_write_t display_config_dsi_01_init_03[14] = {
{sizeof(uint32_t) * DSI_DCS_CMDS, 0}, {sizeof(uint32_t) * DSI_DCS_CMDS, 0},
{sizeof(uint32_t) * DSI_PKT_SEQ_0_LO, 0}, {sizeof(uint32_t) * DSI_PKT_SEQ_0_LO, 0},
{sizeof(uint32_t) * DSI_PKT_SEQ_1_LO, 0}, {sizeof(uint32_t) * DSI_PKT_SEQ_1_LO, 0},
@ -173,6 +173,7 @@ static const register_write_t display_config_dsi_01_init_03[13] = {
{sizeof(uint32_t) * DSI_PKT_SEQ_3_HI, 0}, {sizeof(uint32_t) * DSI_PKT_SEQ_3_HI, 0},
{sizeof(uint32_t) * DSI_PKT_SEQ_4_HI, 0}, {sizeof(uint32_t) * DSI_PKT_SEQ_4_HI, 0},
{sizeof(uint32_t) * DSI_PKT_SEQ_5_HI, 0}, {sizeof(uint32_t) * DSI_PKT_SEQ_5_HI, 0},
{sizeof(uint32_t) * DSI_CONTROL, 0},
}; };
static const register_write_t display_config_dsi_01_init_04_erista[0] = { static const register_write_t display_config_dsi_01_init_04_erista[0] = {
@ -189,8 +190,7 @@ static const register_write_t display_config_dsi_01_init_04_mariko[7] = {
{sizeof(uint32_t) * DSI_PAD_CONTROL_7_MARIKO, 0}, {sizeof(uint32_t) * DSI_PAD_CONTROL_7_MARIKO, 0},
}; };
static const register_write_t display_config_dsi_01_init_05[11] = { static const register_write_t display_config_dsi_01_init_05[10] = {
{sizeof(uint32_t) * DSI_CONTROL, 0},
{sizeof(uint32_t) * DSI_PAD_CONTROL_CD, 0}, {sizeof(uint32_t) * DSI_PAD_CONTROL_CD, 0},
{sizeof(uint32_t) * DSI_SOL_DELAY, 0x18}, {sizeof(uint32_t) * DSI_SOL_DELAY, 0x18},
{sizeof(uint32_t) * DSI_MAX_THRESHOLD, 0x1E0}, {sizeof(uint32_t) * DSI_MAX_THRESHOLD, 0x1E0},

8
sept/sept-secondary/src/di.c
View file

@ -120,9 +120,9 @@ void display_init_erista(void) {
do_register_writes(DI_BASE, display_config_dc_01, 94); do_register_writes(DI_BASE, display_config_dc_01, 94);
do_register_writes(DSI_BASE, display_config_dsi_01_init_01, 8); do_register_writes(DSI_BASE, display_config_dsi_01_init_01, 8);
do_register_writes(DSI_BASE, display_config_dsi_01_init_02_erista, 1); do_register_writes(DSI_BASE, display_config_dsi_01_init_02_erista, 1);
do_register_writes(DSI_BASE, display_config_dsi_01_init_03, 13); do_register_writes(DSI_BASE, display_config_dsi_01_init_03, 14);
do_register_writes(DSI_BASE, display_config_dsi_01_init_04_erista, 0); do_register_writes(DSI_BASE, display_config_dsi_01_init_04_erista, 0);
do_register_writes(DSI_BASE, display_config_dsi_01_init_05, 11); do_register_writes(DSI_BASE, display_config_dsi_01_init_05, 10);
do_register_writes(DSI_BASE, display_config_dsi_phy_timing_erista, 1); do_register_writes(DSI_BASE, display_config_dsi_phy_timing_erista, 1);
do_register_writes(DSI_BASE, display_config_dsi_01_init_06, 12); do_register_writes(DSI_BASE, display_config_dsi_01_init_06, 12);
do_register_writes(DSI_BASE, display_config_dsi_phy_timing_erista, 1); do_register_writes(DSI_BASE, display_config_dsi_phy_timing_erista, 1);
@ -276,9 +276,9 @@ void display_init_mariko(void) {
do_register_writes(DI_BASE, display_config_dc_01, 94); do_register_writes(DI_BASE, display_config_dc_01, 94);
do_register_writes(DSI_BASE, display_config_dsi_01_init_01, 8); do_register_writes(DSI_BASE, display_config_dsi_01_init_01, 8);
do_register_writes(DSI_BASE, display_config_dsi_01_init_02_mariko, 1); do_register_writes(DSI_BASE, display_config_dsi_01_init_02_mariko, 1);
do_register_writes(DSI_BASE, display_config_dsi_01_init_03, 13); do_register_writes(DSI_BASE, display_config_dsi_01_init_03, 14);
do_register_writes(DSI_BASE, display_config_dsi_01_init_04_mariko, 7); do_register_writes(DSI_BASE, display_config_dsi_01_init_04_mariko, 7);
do_register_writes(DSI_BASE, display_config_dsi_01_init_05, 11); do_register_writes(DSI_BASE, display_config_dsi_01_init_05, 10);
do_register_writes(DSI_BASE, display_config_dsi_phy_timing_mariko, 1); do_register_writes(DSI_BASE, display_config_dsi_phy_timing_mariko, 1);
do_register_writes(DSI_BASE, display_config_dsi_01_init_06, 12); do_register_writes(DSI_BASE, display_config_dsi_01_init_06, 12);
do_register_writes(DSI_BASE, display_config_dsi_phy_timing_mariko, 1); do_register_writes(DSI_BASE, display_config_dsi_phy_timing_mariko, 1);

6
sept/sept-secondary/src/di.inl
View file

@ -159,7 +159,7 @@ static const register_write_t display_config_dsi_01_init_02_mariko[1] = {
{sizeof(uint32_t) * DSI_INIT_SEQ_DATA_15_MARIKO, 0x0}, {sizeof(uint32_t) * DSI_INIT_SEQ_DATA_15_MARIKO, 0x0},
}; };
static const register_write_t display_config_dsi_01_init_03[13] = { static const register_write_t display_config_dsi_01_init_03[14] = {
{sizeof(uint32_t) * DSI_DCS_CMDS, 0}, {sizeof(uint32_t) * DSI_DCS_CMDS, 0},
{sizeof(uint32_t) * DSI_PKT_SEQ_0_LO, 0}, {sizeof(uint32_t) * DSI_PKT_SEQ_0_LO, 0},
{sizeof(uint32_t) * DSI_PKT_SEQ_1_LO, 0}, {sizeof(uint32_t) * DSI_PKT_SEQ_1_LO, 0},
@ -173,6 +173,7 @@ static const register_write_t display_config_dsi_01_init_03[13] = {
{sizeof(uint32_t) * DSI_PKT_SEQ_3_HI, 0}, {sizeof(uint32_t) * DSI_PKT_SEQ_3_HI, 0},
{sizeof(uint32_t) * DSI_PKT_SEQ_4_HI, 0}, {sizeof(uint32_t) * DSI_PKT_SEQ_4_HI, 0},
{sizeof(uint32_t) * DSI_PKT_SEQ_5_HI, 0}, {sizeof(uint32_t) * DSI_PKT_SEQ_5_HI, 0},
{sizeof(uint32_t) * DSI_CONTROL, 0},
}; };
static const register_write_t display_config_dsi_01_init_04_erista[0] = { static const register_write_t display_config_dsi_01_init_04_erista[0] = {
@ -189,8 +190,7 @@ static const register_write_t display_config_dsi_01_init_04_mariko[7] = {
{sizeof(uint32_t) * DSI_PAD_CONTROL_7_MARIKO, 0}, {sizeof(uint32_t) * DSI_PAD_CONTROL_7_MARIKO, 0},
}; };
static const register_write_t display_config_dsi_01_init_05[11] = { static const register_write_t display_config_dsi_01_init_05[10] = {
{sizeof(uint32_t) * DSI_CONTROL, 0},
{sizeof(uint32_t) * DSI_PAD_CONTROL_CD, 0}, {sizeof(uint32_t) * DSI_PAD_CONTROL_CD, 0},
{sizeof(uint32_t) * DSI_SOL_DELAY, 0x18}, {sizeof(uint32_t) * DSI_SOL_DELAY, 0x18},
{sizeof(uint32_t) * DSI_MAX_THRESHOLD, 0x1E0}, {sizeof(uint32_t) * DSI_MAX_THRESHOLD, 0x1E0},