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https://github.com/Atmosphere-NX/Atmosphere.git
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kern: add debug logging on smmu error interrupt
This commit is contained in:
Michael Scire
SciresM
parent
34dc062c11
commit
acdce230da
1 changed files with 255 additions and 8 deletions
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@ -16,6 +16,10 @@
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#include <mesosphere.hpp>
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#include "kern_mc_registers.hpp"
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#if defined(MESOSPHERE_BUILD_FOR_DEBUGGING) || defined(MESOSPHERE_BUILD_FOR_AUDITING)
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#define MESOSPHERE_ENABLE_MEMORY_CONTROLLER_INTERRUPT
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#endif
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namespace ams::kern::board::nintendo::nx {
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namespace {
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@ -332,13 +336,13 @@ namespace ams::kern::board::nintendo::nx {
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};
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/* Globals. */
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KLightLock g_lock;
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u8 g_reserved_asid;
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KPhysicalAddress g_memory_controller_address;
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KPhysicalAddress g_reserved_table_phys_addr;
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KDeviceAsidManager g_asid_manager;
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u32 g_saved_page_tables[AsidCount];
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u32 g_saved_asid_registers[ams::svc::DeviceName_Count];
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constinit KLightLock g_lock;
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constinit u8 g_reserved_asid;
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constinit KPhysicalAddress g_memory_controller_address;
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constinit KPhysicalAddress g_reserved_table_phys_addr;
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constinit KDeviceAsidManager g_asid_manager;
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constinit u32 g_saved_page_tables[AsidCount];
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constinit u32 g_saved_asid_registers[ams::svc::DeviceName_Count];
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/* Memory controller access functionality. */
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void WriteMcRegister(size_t offset, u32 value) {
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@ -349,6 +353,237 @@ namespace ams::kern::board::nintendo::nx {
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return KSystemControl::ReadRegisterPrivileged(GetInteger(g_memory_controller_address) + offset);
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}
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/* Memory controller interrupt functionality. */
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constexpr const char * const MemoryControllerClientNames[138] = {
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[ 0] = "csr_ptcr (ptc)",
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[ 1] = "csr_display0a (dc)",
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[ 2] = "csr_display0ab (dcb)",
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[ 3] = "csr_display0b (dc)",
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[ 4] = "csr_display0bb (dcb)",
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[ 5] = "csr_display0c (dc)",
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[ 6] = "csr_display0cb (dcb)",
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[ 7] = "Unknown Client",
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[ 8] = "Unknown Client",
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[ 9] = "Unknown Client",
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[ 10] = "Unknown Client",
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[ 11] = "Unknown Client",
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[ 12] = "Unknown Client",
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[ 13] = "Unknown Client",
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[ 14] = "csr_afir (afi)",
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[ 15] = "csr_avpcarm7r (avpc)",
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[ 16] = "csr_displayhc (dc)",
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[ 17] = "csr_displayhcb (dcb)",
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[ 18] = "Unknown Client",
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[ 19] = "Unknown Client",
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[ 20] = "Unknown Client",
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[ 21] = "csr_hdar (hda)",
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[ 22] = "csr_host1xdmar (hc)",
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[ 23] = "csr_host1xr (hc)",
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[ 24] = "Unknown Client",
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[ 25] = "Unknown Client",
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[ 26] = "Unknown Client",
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[ 27] = "Unknown Client",
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[ 28] = "csr_nvencsrd (nvenc)",
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[ 29] = "csr_ppcsahbdmar (ppcs)",
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[ 30] = "csr_ppcsahbslvr (ppcs)",
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[ 31] = "csr_satar (sata)",
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[ 32] = "Unknown Client",
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[ 33] = "Unknown Client",
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[ 34] = "Unknown Client",
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[ 35] = "Unknown Client",
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[ 36] = "Unknown Client",
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[ 37] = "Unknown Client",
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[ 38] = "Unknown Client",
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[ 39] = "csr_mpcorer (cpu)",
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[ 40] = "Unknown Client",
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[ 41] = "Unknown Client",
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[ 42] = "Unknown Client",
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[ 43] = "csw_nvencswr (nvenc)",
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[ 44] = "Unknown Client",
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[ 45] = "Unknown Client",
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[ 46] = "Unknown Client",
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[ 47] = "Unknown Client",
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[ 48] = "Unknown Client",
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[ 49] = "csw_afiw (afi)",
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[ 50] = "csw_avpcarm7w (avpc)",
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[ 51] = "Unknown Client",
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[ 52] = "Unknown Client",
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[ 53] = "csw_hdaw (hda)",
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[ 54] = "csw_host1xw (hc)",
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[ 55] = "Unknown Client",
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[ 56] = "Unknown Client",
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[ 57] = "csw_mpcorew (cpu)",
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[ 58] = "Unknown Client",
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[ 59] = "csw_ppcsahbdmaw (ppcs)",
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[ 60] = "csw_ppcsahbslvw (ppcs)",
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[ 61] = "csw_sataw (sata)",
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[ 62] = "Unknown Client",
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[ 63] = "Unknown Client",
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[ 64] = "Unknown Client",
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[ 65] = "Unknown Client",
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[ 66] = "Unknown Client",
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[ 67] = "Unknown Client",
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[ 68] = "csr_ispra (isp2)",
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[ 69] = "Unknown Client",
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[ 70] = "csw_ispwa (isp2)",
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[ 71] = "csw_ispwb (isp2)",
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[ 72] = "Unknown Client",
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[ 73] = "Unknown Client",
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[ 74] = "csr_xusb_hostr (xusb_host)",
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[ 75] = "csw_xusb_hostw (xusb_host)",
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[ 76] = "csr_xusb_devr (xusb_dev)",
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[ 77] = "csw_xusb_devw (xusb_dev)",
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[ 78] = "csr_isprab (isp2b)",
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[ 79] = "Unknown Client",
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[ 80] = "csw_ispwab (isp2b)",
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[ 81] = "csw_ispwbb (isp2b)",
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[ 82] = "Unknown Client",
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[ 83] = "Unknown Client",
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[ 84] = "csr_tsecsrd (tsec)",
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[ 85] = "csw_tsecswr (tsec)",
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[ 86] = "csr_a9avpscr (a9avp)",
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[ 87] = "csw_a9avpscw (a9avp)",
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[ 88] = "csr_gpusrd (gpu)",
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[ 89] = "csw_gpuswr (gpu)",
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[ 90] = "csr_displayt (dc)",
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[ 91] = "Unknown Client",
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[ 92] = "Unknown Client",
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[ 93] = "Unknown Client",
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[ 94] = "Unknown Client",
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[ 95] = "Unknown Client",
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[ 96] = "csr_sdmmcra (sdmmc1a)",
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[ 97] = "csr_sdmmcraa (sdmmc2a)",
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[ 98] = "csr_sdmmcr (sdmmc3a)",
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[ 99] = "csr_sdmmcrab (sdmmc4a)",
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[100] = "csw_sdmmcwa (sdmmc1a)",
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[101] = "csw_sdmmcwaa (sdmmc2a)",
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[102] = "csw_sdmmcw (sdmmc3a)",
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[103] = "csw_sdmmcwab (sdmmc4a)",
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[104] = "Unknown Client",
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[105] = "Unknown Client",
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[106] = "Unknown Client",
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[107] = "Unknown Client",
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[108] = "csr_vicsrd (vic)",
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[109] = "csw_vicswr (vic)",
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[110] = "Unknown Client",
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[111] = "Unknown Client",
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[112] = "Unknown Client",
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[113] = "Unknown Client",
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[114] = "csw_viw (vi)",
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[115] = "csr_displayd (dc)",
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[116] = "Unknown Client",
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[117] = "Unknown Client",
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[118] = "Unknown Client",
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[119] = "Unknown Client",
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[120] = "csr_nvdecsrd (nvdec)",
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[121] = "csw_nvdecswr (nvdec)",
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[122] = "csr_aper (ape)",
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[123] = "csw_apew (ape)",
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[124] = "Unknown Client",
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[125] = "Unknown Client",
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[126] = "csr_nvjpgsrd (nvjpg)",
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[127] = "csw_nvjpgswr (nvjpg)",
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[128] = "csr_sesrd (se)",
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[129] = "csw_seswr (se)",
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[130] = "csr_axiapr (axiap)",
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[131] = "csw_axiapw (axiap)",
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[132] = "csr_etrr (etr)",
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[133] = "csw_etrw (etr)",
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[134] = "csr_tsecsrdb (tsecb)",
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[135] = "csw_tsecswrb (tsecb)",
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[136] = "csr_gpusrd2 (gpu)",
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[137] = "csw_gpuswr2 (gpu)",
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};
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constexpr const char * GetMemoryControllerClientName(size_t i) {
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if (i < util::size(MemoryControllerClientNames)) {
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return MemoryControllerClientNames[i];
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}
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return "Unknown Client";
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}
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constexpr const char * const MemoryControllerErrorTypes[8] = {
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"RSVD",
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"Unknown",
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"DECERR_EMEM",
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"SECURITY_TRUSTZONE",
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"SECURITY_CARVEOUT",
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"Unknown",
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"INVALID_SMMU_PAGE",
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"Unknown",
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};
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class KMemoryControllerInterruptTask : public KInterruptTask {
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public:
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constexpr KMemoryControllerInterruptTask() : KInterruptTask() { /* ... */ }
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virtual KInterruptTask *OnInterrupt(s32 interrupt_id) override {
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MESOSPHERE_UNUSED(interrupt_id);
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return this;
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}
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virtual void DoTask() override {
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#if defined(MESOSPHERE_ENABLE_MEMORY_CONTROLLER_INTERRUPT)
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{
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/* Clear the interrupt when we're done. */
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ON_SCOPE_EXIT { };
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/* Get and clear the interrupt status. */
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u32 int_status, err_status, err_adr;
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{
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int_status = ReadMcRegister(MC_INTSTATUS);
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err_status = ReadMcRegister(MC_ERR_STATUS);
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err_adr = ReadMcRegister(MC_ERR_ADR);
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WriteMcRegister(MC_INTSTATUS, int_status);
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}
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/* Print the interrupt. */
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{
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constexpr auto GetBits = [] ALWAYS_INLINE_LAMBDA (u32 value, size_t ofs, size_t count) {
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return (value >> ofs) & ((1u << count) - 1);
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};
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constexpr auto GetBit = [GetBits] ALWAYS_INLINE_LAMBDA (u32 value, size_t ofs) {
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return (value >> ofs) & 1u;
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};
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MESOSPHERE_RELEASE_LOG("sMMU error interrupt\n");
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MESOSPHERE_RELEASE_LOG(" MC_INTSTATUS=%08x\n", int_status);
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MESOSPHERE_RELEASE_LOG(" DECERR_GENERALIZED_CARVEOUT=%d\n", GetBit(int_status, 17));
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MESOSPHERE_RELEASE_LOG(" DECERR_MTS=%d\n", GetBit(int_status, 16));
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MESOSPHERE_RELEASE_LOG(" SECERR_SEC=%d\n", GetBit(int_status, 13));
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MESOSPHERE_RELEASE_LOG(" DECERR_VPR=%d\n", GetBit(int_status, 12));
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MESOSPHERE_RELEASE_LOG(" INVALID_APB_ASID_UPDATE=%d\n", GetBit(int_status, 11));
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MESOSPHERE_RELEASE_LOG(" INVALID_SMMU_PAGE=%d\n", GetBit(int_status, 10));
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MESOSPHERE_RELEASE_LOG(" ARBITRATION_EMEM=%d\n", GetBit(int_status, 9));
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MESOSPHERE_RELEASE_LOG(" SECURITY_VIOLATION=%d\n", GetBit(int_status, 8));
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MESOSPHERE_RELEASE_LOG(" DECERR_EMEM=%d\n", GetBit(int_status, 6));
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MESOSPHERE_RELEASE_LOG(" MC_ERRSTATUS=%08x\n", err_status);
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MESOSPHERE_RELEASE_LOG(" ERR_TYPE=%d (%s)\n", GetBits(err_status, 28, 3), MemoryControllerErrorTypes[GetBits(err_status, 28, 3)]);
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MESOSPHERE_RELEASE_LOG(" ERR_INVALID_SMMU_PAGE_READABLE=%d\n", GetBit (err_status, 27));
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MESOSPHERE_RELEASE_LOG(" ERR_INVALID_SMMU_PAGE_WRITABLE=%d\n", GetBit (err_status, 26));
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MESOSPHERE_RELEASE_LOG(" ERR_INVALID_SMMU_NONSECURE=%d\n", GetBit (err_status, 25));
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MESOSPHERE_RELEASE_LOG(" ERR_ADR_HI=%x\n", GetBits(err_status, 20, 2));
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MESOSPHERE_RELEASE_LOG(" ERR_SWAP=%d\n", GetBit (err_status, 18));
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MESOSPHERE_RELEASE_LOG(" ERR_SECURITY=%d %s\n", GetBit (err_status, 17), GetBit(err_status, 17) ? "SECURE" : "NONSECURE");
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MESOSPHERE_RELEASE_LOG(" ERR_RW=%d %s\n", GetBit (err_status, 16), GetBit(err_status, 16) ? "WRITE" : "READ");
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MESOSPHERE_RELEASE_LOG(" ERR_ADR1=%x\n", GetBits(err_status, 12, 3));
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MESOSPHERE_RELEASE_LOG(" ERR_ID=%d %s\n", GetBits(err_status, 0, 8), GetMemoryControllerClientName(GetBits(err_status, 0, 8)));
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MESOSPHERE_RELEASE_LOG(" MC_ERRADR=%08x\n", err_adr);
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MESOSPHERE_RELEASE_LOG(" ERR_ADR=%lx\n", (static_cast<u64>(GetBits(err_status, 20, 2)) << 32) | static_cast<u64>(err_adr));
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MESOSPHERE_RELEASE_LOG("\n");
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}
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}
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#endif
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}
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};
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/* Interrupt task global. */
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constinit KMemoryControllerInterruptTask g_mc_interrupt_task;
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/* Memory controller utilities. */
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void SmmuSynchronizationBarrier() {
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ReadMcRegister(MC_SMMU_CONFIG);
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}
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@ -452,11 +687,23 @@ namespace ams::kern::board::nintendo::nx {
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/* Clear int status. */
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WriteMcRegister(MC_INTSTATUS, ReadMcRegister(MC_INTSTATUS));
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/* If we're setting an interrupt handler, unmask all interrupts. */
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#if defined(MESOSPHERE_ENABLE_MEMORY_CONTROLLER_INTERRUPT)
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{
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WriteMcRegister(MC_INTMASK, 0x33D40);
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}
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#endif
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/* Enable the SMMU */
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WriteMcRegister(MC_SMMU_CONFIG, 1);
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SmmuSynchronizationBarrier();
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/* TODO: Install interrupt handler. */
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/* Install interrupt handler. */
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#if defined(MESOSPHERE_ENABLE_MEMORY_CONTROLLER_INTERRUPT)
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{
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Kernel::GetInterruptManager().BindHandler(std::addressof(g_mc_interrupt_task), KInterruptName_MemoryController, GetCurrentCoreId(), KInterruptController::PriorityLevel_High, true, true);
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}
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#endif
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}
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void KDevicePageTable::Lock() {
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