From a85e20bcea446ae69c6815a894fb5e28f5446348 Mon Sep 17 00:00:00 2001 From: Michael Scire Date: Tue, 17 Dec 2019 07:07:35 -0800 Subject: [PATCH] kernel_ldr::cpu: prevent reordering around barrier instructions --- .../include/mesosphere/arch/arm64/kern_cpu.hpp | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/libraries/libmesosphere/include/mesosphere/arch/arm64/kern_cpu.hpp b/libraries/libmesosphere/include/mesosphere/arch/arm64/kern_cpu.hpp index 4a674cd3f..eff9bf847 100644 --- a/libraries/libmesosphere/include/mesosphere/arch/arm64/kern_cpu.hpp +++ b/libraries/libmesosphere/include/mesosphere/arch/arm64/kern_cpu.hpp @@ -21,19 +21,19 @@ namespace ams::kern::arm64::cpu { /* Helpers for managing memory state. */ ALWAYS_INLINE void DataSynchronizationBarrier() { - __asm__ __volatile__("dsb sy"); + __asm__ __volatile__("dsb sy" ::: "memory"); } ALWAYS_INLINE void DataSynchronizationBarrierInnerShareable() { - __asm__ __volatile__("dsb ish"); + __asm__ __volatile__("dsb ish" ::: "memory"); } ALWAYS_INLINE void DataMemoryBarrier() { - __asm__ __volatile__("dmb sy"); + __asm__ __volatile__("dmb sy" ::: "memory"); } ALWAYS_INLINE void InstructionMemoryBarrier() { - __asm__ __volatile__("isb"); + __asm__ __volatile__("isb" ::: "memory"); } ALWAYS_INLINE void EnsureInstructionConsistency() {