From 669564b02249038c81a01a39b88e9cb409599814 Mon Sep 17 00:00:00 2001 From: Michael Scire Date: Sat, 21 Aug 2021 18:00:44 -0700 Subject: [PATCH] fusee-cpp: implement SecureInitialize besides InitializeClock() --- .../source/fusee_secure_initialize.cpp | 29 ++- libraries/libexosphere/include/exosphere.hpp | 1 + .../libexosphere/include/exosphere/pinmux.hpp | 6 + .../libexosphere/include/exosphere/pmic.hpp | 6 +- .../include/exosphere/pmic_setup.hpp | 27 +++ .../libexosphere/source/pinmux/pinmux_api.cpp | 76 ++++++ .../libexosphere/source/pmic/pmic_api.cpp | 60 ++++- .../include/vapours/tegra/tegra_apb_misc.hpp | 2 + .../include/vapours/tegra/tegra_pinmux.hpp | 5 + .../include/vapours/tegra/tegra_pmc.hpp | 217 ++++++++++-------- 10 files changed, 314 insertions(+), 115 deletions(-) create mode 100644 libraries/libexosphere/include/exosphere/pmic_setup.hpp diff --git a/fusee_cpp/program/source/fusee_secure_initialize.cpp b/fusee_cpp/program/source/fusee_secure_initialize.cpp index 90f556467..e4bbbdf03 100644 --- a/fusee_cpp/program/source/fusee_secure_initialize.cpp +++ b/fusee_cpp/program/source/fusee_secure_initialize.cpp @@ -23,6 +23,7 @@ namespace ams::nxboot { constexpr inline const uintptr_t CLKRST = secmon::MemoryRegionPhysicalDeviceClkRst.GetAddress(); constexpr inline const uintptr_t PMC = secmon::MemoryRegionPhysicalDevicePmc.GetAddress(); + constexpr inline const uintptr_t APB = secmon::MemoryRegionPhysicalDeviceApbMisc.GetAddress(); constexpr inline const uintptr_t AHB = AHB_ARBC(0); constexpr inline const uintptr_t I2S = I2S_REG(0); constexpr inline const uintptr_t DISP1 = secmon::MemoryRegionPhysicalDeviceDisp1.GetAddress(); @@ -166,7 +167,18 @@ namespace ams::nxboot { } void InitializePinmux(fuse::HardwareType hw_type) { - /* TODO */ + /* Clear global pinmux control register */ + reg::Write(APB + APB_MISC_PP_PINMUX_GLOBAL_0, 0); + + /* Perform initial pinmux setup. */ + pinmux::SetupFirst(hw_type); + + /* Setup important pinmux devices. */ + pinmux::SetupI2c1(); + pinmux::SetupI2c5(); + pinmux::SetupUartA(); + pinmux::SetupVolumeButton(); + pinmux::SetupHomeButton(); } @@ -211,10 +223,10 @@ namespace ams::nxboot { i2c::Initialize(i2c::Port_5); /* Configure pmic system setting. */ - pmic::SetSystemSetting(); + pmic::SetSystemSetting(soc_type); /* Enable VDD core */ - pmic::EnableVddCore(); + pmic::EnableVddCore(soc_type); /* On hoag, enable Ldo8 */ if (hw_type == fuse::HardwareType_Hoag) { @@ -229,6 +241,17 @@ namespace ams::nxboot { CLK_RST_REG_BITS_ENUM(SCLK_BURST_POLICY_SWAKEUP_IRQ_SOURCE, PLLP_OUT0), CLK_RST_REG_BITS_ENUM(SCLK_BURST_POLICY_SWAKEUP_RUN_SOURCE, PLLP_OUT0), CLK_RST_REG_BITS_ENUM(SCLK_BURST_POLICY_SWAKEUP_IDLE_SOURCE, PLLP_OUT0)); + + /* Do mariko-only TZRAM configuration. */ + if (soc_type == fuse::SocType_Mariko) { + reg::ReadWrite(PMC + APBDEV_PMC_TZRAM_PWR_CNTRL, PMC_REG_BITS_VALUE(TZRAM_PWR_CNTRL_TZRAM_SD, 0)); + + reg::Write(PMC + APBDEV_PMC_TZRAM_NON_SEC_DISABLE, PMC_REG_BITS_ENUM(TZRAM_NON_SEC_DISABLE_SD_WRITE, ON), + PMC_REG_BITS_ENUM(TZRAM_NON_SEC_DISABLE_SD_READ, ON)); + + reg::Write(PMC + APBDEV_PMC_TZRAM_SEC_DISABLE, PMC_REG_BITS_ENUM(TZRAM_SEC_DISABLE_SD_WRITE, ON), + PMC_REG_BITS_ENUM(TZRAM_SEC_DISABLE_SD_READ, ON)); + } } } diff --git a/libraries/libexosphere/include/exosphere.hpp b/libraries/libexosphere/include/exosphere.hpp index 5fe60639c..a993ddfb6 100644 --- a/libraries/libexosphere/include/exosphere.hpp +++ b/libraries/libexosphere/include/exosphere.hpp @@ -34,6 +34,7 @@ #include #include #include +#include #include #include #include diff --git a/libraries/libexosphere/include/exosphere/pinmux.hpp b/libraries/libexosphere/include/exosphere/pinmux.hpp index f79035b27..ef3fa1b45 100644 --- a/libraries/libexosphere/include/exosphere/pinmux.hpp +++ b/libraries/libexosphere/include/exosphere/pinmux.hpp @@ -15,15 +15,21 @@ */ #pragma once #include +#include namespace ams::pinmux { void SetRegisterAddress(uintptr_t pinmux_address, uintptr_t gpio_address); + void SetupFirst(fuse::HardwareType hw_type); + void SetupUartA(); void SetupUartB(); void SetupUartC(); void SetupI2c1(); void SetupI2c5(); + void SetupVolumeButton(); + void SetupHomeButton(); + } diff --git a/libraries/libexosphere/include/exosphere/pmic.hpp b/libraries/libexosphere/include/exosphere/pmic.hpp index 2fc92ff70..aa8192a23 100644 --- a/libraries/libexosphere/include/exosphere/pmic.hpp +++ b/libraries/libexosphere/include/exosphere/pmic.hpp @@ -36,8 +36,4 @@ namespace ams::pmic { bool IsAcOk(); bool IsPowerButtonPressed(); - void SetSystemSetting(); - void EnableVddCore(); - void EnableLdo8(); - -} \ No newline at end of file +} diff --git a/libraries/libexosphere/include/exosphere/pmic_setup.hpp b/libraries/libexosphere/include/exosphere/pmic_setup.hpp new file mode 100644 index 000000000..38466504c --- /dev/null +++ b/libraries/libexosphere/include/exosphere/pmic_setup.hpp @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2018-2020 Atmosphère-NX + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#pragma once +#include +#include +#include + +namespace ams::pmic { + + void SetSystemSetting(fuse::SocType soc_type); + void EnableVddCore(fuse::SocType soc_type); + void EnableLdo8(); + +} \ No newline at end of file diff --git a/libraries/libexosphere/source/pinmux/pinmux_api.cpp b/libraries/libexosphere/source/pinmux/pinmux_api.cpp index 3559541cd..9ba7c0d1e 100644 --- a/libraries/libexosphere/source/pinmux/pinmux_api.cpp +++ b/libraries/libexosphere/source/pinmux/pinmux_api.cpp @@ -22,6 +22,51 @@ namespace ams::pinmux { constinit uintptr_t g_pinmux_address = secmon::MemoryRegionPhysicalDeviceApbMisc.GetAddress(); constinit uintptr_t g_gpio_address = secmon::MemoryRegionPhysicalDeviceGpio.GetAddress(); + void SetupFirstImpl(bool tx_cross_ext_con) { + if (tx_cross_ext_con) { + reg::Write(g_pinmux_address + PINMUX_AUX_UART2_TX, PINMUX_REG_BITS_ENUM(AUX_UART2_PM, UARTB), + PINMUX_REG_BITS_ENUM(AUX_PUPD, NONE), + PINMUX_REG_BITS_ENUM(AUX_TRISTATE, PASSTHROUGH), + PINMUX_REG_BITS_ENUM(AUX_E_INPUT, DISABLE), + PINMUX_REG_BITS_ENUM(AUX_LOCK, DISABLE), + PINMUX_REG_BITS_ENUM(AUX_E_OD, DISABLE)); + + reg::Write(g_pinmux_address + PINMUX_AUX_UART3_TX, PINMUX_REG_BITS_ENUM(AUX_UART3_PM, UARTC), + PINMUX_REG_BITS_ENUM(AUX_PUPD, NONE), + PINMUX_REG_BITS_ENUM(AUX_TRISTATE, PASSTHROUGH), + PINMUX_REG_BITS_ENUM(AUX_E_INPUT, DISABLE), + PINMUX_REG_BITS_ENUM(AUX_LOCK, DISABLE), + PINMUX_REG_BITS_ENUM(AUX_E_OD, DISABLE)); + + /* Configure GPIO for Uart-B/Uart-C. */ + reg::ReadWrite(g_gpio_address + 0x108, REG_BITS_VALUE(0, 1, 1)); + reg::ReadWrite(g_gpio_address + 0x00C, REG_BITS_VALUE(1, 1, 1)); + reg::ReadWrite(g_gpio_address + 0x118, REG_BITS_VALUE(0, 1, 0)); + reg::ReadWrite(g_gpio_address + 0x01C, REG_BITS_VALUE(1, 1, 0)); + } + + /* Configure PE6/PH6 */ + reg::Write(g_pinmux_address + PINMUX_AUX_GPIO_PE6, PINMUX_REG_BITS_ENUM(AUX_GPIO_PE6_PM, RSVD0), + PINMUX_REG_BITS_ENUM(AUX_PUPD, NONE), + PINMUX_REG_BITS_ENUM(AUX_TRISTATE, PASSTHROUGH), + PINMUX_REG_BITS_ENUM(AUX_E_INPUT, ENABLE), + PINMUX_REG_BITS_ENUM(AUX_LOCK, DISABLE), + PINMUX_REG_BITS_ENUM(AUX_E_OD, DISABLE)); + + reg::Write(g_pinmux_address + PINMUX_AUX_GPIO_PH6, PINMUX_REG_BITS_ENUM(AUX_GPIO_PH6_PM, RSVD0), + PINMUX_REG_BITS_ENUM(AUX_PUPD, NONE), + PINMUX_REG_BITS_ENUM(AUX_TRISTATE, PASSTHROUGH), + PINMUX_REG_BITS_ENUM(AUX_E_INPUT, ENABLE), + PINMUX_REG_BITS_ENUM(AUX_LOCK, DISABLE), + PINMUX_REG_BITS_ENUM(AUX_E_OD, DISABLE)); + + /* Configure GPIO E6/H6. */ + reg::ReadWrite(g_gpio_address + 0x100, REG_BITS_VALUE(6, 1, 1)); + reg::ReadWrite(g_gpio_address + 0x10C, REG_BITS_VALUE(6, 1, 1)); + reg::ReadWrite(g_gpio_address + 0x110, REG_BITS_VALUE(6, 1, 0)); + reg::ReadWrite(g_gpio_address + 0x11C, REG_BITS_VALUE(6, 1, 0)); + } + } void SetRegisterAddress(uintptr_t pinmux_address, uintptr_t gpio_address) { @@ -29,6 +74,23 @@ namespace ams::pinmux { g_gpio_address = gpio_address; } + void SetupFirst(fuse::HardwareType hw_type) { + switch (hw_type) { + case fuse::HardwareType_Icosa: + case fuse::HardwareType_Iowa: + case fuse::HardwareType_Aula: + SetupFirstImpl(true); + break; + case fuse::HardwareType_Hoag: + case fuse::HardwareType_Calcio: + SetupFirstImpl(false); + break; + case fuse::HardwareType_Copper: + case fuse::HardwareType_Undefined: + break; + } + } + void SetupUartA() { /* Get the registers. */ const uintptr_t PINMUX = g_pinmux_address; @@ -180,4 +242,18 @@ namespace ams::pinmux { PINMUX_REG_BITS_ENUM(AUX_E_OD, DISABLE)); } + void SetupVolumeButton() { + /* Configure VOL_UP/VOL_DOWN */ + reg::ReadWrite(g_gpio_address + 0x50C, REG_BITS_VALUE(6, 1, 1)); + reg::ReadWrite(g_gpio_address + 0x50C, REG_BITS_VALUE(7, 1, 1)); + reg::ReadWrite(g_gpio_address + 0x51C, REG_BITS_VALUE(6, 1, 0)); + reg::ReadWrite(g_gpio_address + 0x51C, REG_BITS_VALUE(7, 1, 0)); + } + + void SetupHomeButton() { + /* Configure BUTTON_HOME */ + reg::ReadWrite(g_gpio_address + 0x600, REG_BITS_VALUE(1, 1, 1)); + reg::ReadWrite(g_gpio_address + 0x610, REG_BITS_VALUE(1, 1, 0)); + } + } \ No newline at end of file diff --git a/libraries/libexosphere/source/pmic/pmic_api.cpp b/libraries/libexosphere/source/pmic/pmic_api.cpp index 84c8fbf64..37dab92d7 100644 --- a/libraries/libexosphere/source/pmic/pmic_api.cpp +++ b/libraries/libexosphere/source/pmic/pmic_api.cpp @@ -32,10 +32,22 @@ namespace ams::pmic { /* TODO: Find datasheet, link to it instead. */ /* NOTE: Tentatively, Max77620 "mostly" matches https://datasheets.maximintegrated.com/en/ds/MAX77863.pdf. */ /* This does not contain Max77621 documentation, though. */ + constexpr inline int Max77620RegisterCnfgBbc = 0x04; constexpr inline int Max77620RegisterOnOffStat = 0x15; + constexpr inline int Max77620RegisterSd0 = 0x16; + constexpr inline int Max77620RegisterCnfg1Ldo8 = 0x33; constexpr inline int Max77620RegisterGpio0 = 0x36; constexpr inline int Max77620RegisterAmeGpio = 0x40; constexpr inline int Max77620RegisterOnOffCnfg1 = 0x41; + constexpr inline int Max77620RegisterCnfgFps0 = 0x43; + constexpr inline int Max77620RegisterCnfgFps1 = 0x44; + constexpr inline int Max77620RegisterCnfgFps2 = 0x45; + constexpr inline int Max77620RegisterFpsLdo4 = 0x4A; + constexpr inline int Max77620RegisterFpsLdo8 = 0x4E; + constexpr inline int Max77620RegisterFpsSd0 = 0x4F; + constexpr inline int Max77620RegisterFpsSd1 = 0x50; + constexpr inline int Max77620RegisterFpsSd3 = 0x52; + constexpr inline int Max77620RegisterFpsGpio3 = 0x56; constexpr inline int Max77621RegisterVOut = 0x00; constexpr inline int Max77621RegisterVOutDvc = 0x01; @@ -148,6 +160,35 @@ namespace ams::pmic { i2c::SendByte(i2c::Port_5, I2cAddressMax77620Pmic, MAX77620_REG_ONOFFCNFG1, on_off_1_val); } + void SetBackupBatteryConfig() { + i2c::SendByte(i2c::Port_5, I2cAddressMax77620Pmic, Max77620RegisterCnfgBbc, 0x40); + } + + void SetForcePowerOffTimeConfig() { + i2c::SendByte(i2c::Port_5, I2cAddressMax77620Pmic, Max77620RegisterOnOffCnfg1, 0x58); + } + + void SetFlexiblePowerSequencer() { + /* Configure FPS registers. */ + i2c::SendByte(i2c::Port_5, I2cAddressMax77620Pmic, Max77620RegisterCnfgFps0, 0x38); + i2c::SendByte(i2c::Port_5, I2cAddressMax77620Pmic, Max77620RegisterCnfgFps1, 0x3A); + i2c::SendByte(i2c::Port_5, I2cAddressMax77620Pmic, Max77620RegisterCnfgFps2, 0x38); + + i2c::SendByte(i2c::Port_5, I2cAddressMax77620Pmic, Max77620RegisterFpsLdo4, 0x0F); + i2c::SendByte(i2c::Port_5, I2cAddressMax77620Pmic, Max77620RegisterFpsLdo8, 0xC7); + + i2c::SendByte(i2c::Port_5, I2cAddressMax77620Pmic, Max77620RegisterFpsSd0, 0x4F); + i2c::SendByte(i2c::Port_5, I2cAddressMax77620Pmic, Max77620RegisterFpsSd1, 0x29); + i2c::SendByte(i2c::Port_5, I2cAddressMax77620Pmic, Max77620RegisterFpsSd3, 0x1B); + + i2c::SendByte(i2c::Port_5, I2cAddressMax77620Pmic, Max77620RegisterFpsGpio3, 0x22); + } + + void SetVoltage(int reg, int mv) { + const u8 v = ((mv - 600) * 1000) / 12500; + i2c::SendByte(i2c::Port_5, I2cAddressMax77620Pmic, reg, v); + } + } void SetEnBit(Regulator regulator) { @@ -215,15 +256,24 @@ namespace ams::pmic { return (GetPmicOnOffStat() & (1 << 2)) != 0; } - void SetSystemSetting() { - /* TODO */ + void SetSystemSetting(fuse::SocType soc_type) { + SetBackupBatteryConfig(); + SetForcePowerOffTimeConfig(); + if (soc_type == fuse::SocType_Erista) { + SetFlexiblePowerSequencer(); + } } - void EnableVddCore() { - /* TODO */ + + void EnableVddCore(fuse::SocType soc_type) { + if (soc_type == fuse::SocType_Erista) { + SetVoltage(Max77620RegisterSd0, 1125); + } else /* if (soc_type == fuse::SocType_Mariko) */ { + SetVoltage(Max77620RegisterSd0, 1050); + } } void EnableLdo8() { - /* TODO */ + i2c::SendByte(i2c::Port_5, I2cAddressMax77620Pmic, Max77620RegisterCnfg1Ldo8, 0xE8); } } diff --git a/libraries/libvapours/include/vapours/tegra/tegra_apb_misc.hpp b/libraries/libvapours/include/vapours/tegra/tegra_apb_misc.hpp index 47fa9bcca..073de791b 100644 --- a/libraries/libvapours/include/vapours/tegra/tegra_apb_misc.hpp +++ b/libraries/libvapours/include/vapours/tegra/tegra_apb_misc.hpp @@ -23,6 +23,8 @@ #define APB_MISC_PP_CONFIG_CTL (0x024) +#define APB_MISC_PP_PINMUX_GLOBAL_0 (0x040) + #define APB_MISC_GP_ASDBGREG (0x810) #define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL (0xA98) diff --git a/libraries/libvapours/include/vapours/tegra/tegra_pinmux.hpp b/libraries/libvapours/include/vapours/tegra/tegra_pinmux.hpp index 9284ce14b..d21ec79a5 100644 --- a/libraries/libvapours/include/vapours/tegra/tegra_pinmux.hpp +++ b/libraries/libvapours/include/vapours/tegra/tegra_pinmux.hpp @@ -55,6 +55,9 @@ #define PINMUX_AUX_LCD_BL_EN (0x3200) #define PINMUX_AUX_LCD_RST (0x3204) #define PINMUX_AUX_GPIO_PA6 (0x3244) +#define PINMUX_AUX_GPIO_PE6 (0x3248) +#define PINMUX_AUX_GPIO_PH6 (0x3250) + #define PINMUX_REG_BITS_MASK(NAME) REG_NAMED_BITS_MASK (PINMUX, NAME) #define PINMUX_REG_BITS_VALUE(NAME, VALUE) REG_NAMED_BITS_VALUE (PINMUX, NAME, VALUE) @@ -98,3 +101,5 @@ DEFINE_PINMUX_REG_TWO_BIT_ENUM(AUX_DVFS_PWM_PM, 0, RSVD0, CLDVFS, SPI3, RSVD3); DEFINE_PINMUX_REG_TWO_BIT_ENUM(AUX_LCD_BL_PWM_PM, 0, DISPLAYA, PWM0, SOR0, RSVD3); DEFINE_PINMUX_REG_TWO_BIT_ENUM(AUX_GPIO_PA6_PM, 0, SATA, RSVD1, RSVD2, RSVD3); +DEFINE_PINMUX_REG_TWO_BIT_ENUM(AUX_GPIO_PE6_PM, 0, RSVD0, I2S5A, PWM2, RSVD3); +DEFINE_PINMUX_REG_TWO_BIT_ENUM(AUX_GPIO_PH6_PM, 0, RSVD0, RSVD1, RSVD2, RSVD3); diff --git a/libraries/libvapours/include/vapours/tegra/tegra_pmc.hpp b/libraries/libvapours/include/vapours/tegra/tegra_pmc.hpp index 561d44f13..c544fda9c 100644 --- a/libraries/libvapours/include/vapours/tegra/tegra_pmc.hpp +++ b/libraries/libvapours/include/vapours/tegra/tegra_pmc.hpp @@ -21,108 +21,112 @@ #include #include -#define APBDEV_PMC_CNTRL (0x000) -#define APBDEV_PMC_WAKE_MASK (0x00C) -#define APBDEV_PMC_WAKE_LVL (0x010) -#define APBDEV_PMC_WAKE_STATUS (0x014) -#define APBDEV_PMC_DPD_PADS_ORIDE (0x01C) -#define APBDEV_PMC_DPD_SAMPLE (0x020) -#define APBDEV_PMC_DPD_ENABLE (0x024) -#define APBDEV_PMC_CLAMP_STATUS (0x02C) -#define APBDEV_PMC_PWRGATE_TOGGLE (0x030) -#define APBDEV_PMC_REMOVE_CLAMPING_CMD (0x034) -#define APBDEV_PMC_PWRGATE_STATUS (0x038) -#define APBDEV_PMC_PWRGOOD_TIMER (0x03C) -#define APBDEV_PMC_BLINK_TIMER (0x040) -#define APBDEV_PMC_NO_IOPOWER (0x044) -#define APBDEV_PMC_PWR_DET (0x048) -#define APBDEV_PMC_SCRATCH0 (0x050) -#define APBDEV_PMC_SCRATCH1 (0x054) -#define APBDEV_PMC_SCRATCH4 (0x060) -#define APBDEV_PMC_SCRATCH12 (0x080) -#define APBDEV_PMC_SCRATCH13 (0x084) -#define APBDEV_PMC_SCRATCH18 (0x098) -#define APBDEV_PMC_SCRATCH20 (0x0A0) -#define APBDEV_PMC_AUTO_WAKE_LVL_MASK (0x0DC) -#define APBDEV_PMC_WAKE_DELAY (0x0E0) -#define APBDEV_PMC_PWR_DET_VAL (0x0E4) -#define APBDEV_PMC_CRYPTO_OP (0x0F4) -#define APBDEV_PMC_SCRATCH31 (0x118) -#define APBDEV_PMC_SCRATCH32 (0x11C) -#define APBDEV_PMC_SCRATCH33 (0x120) -#define APBDEV_PMC_SCRATCH39 (0x138) -#define APBDEV_PMC_SCRATCH40 (0x13C) -#define APBDEV_PMC_WAKE2_MASK (0x160) -#define APBDEV_PMC_WAKE2_LVL (0x164) -#define APBDEV_PMC_WAKE2_STATUS (0x168) -#define APBDEV_PMC_AUTO_WAKE2_LVL_MASK (0x170) -#define APBDEV_PMC_OSC_EDPD_OVER (0x1A4) -#define APBDEV_PMC_CLK_OUT_CNTRL (0x1A8) -#define APBDEV_PMC_RST_STATUS (0x1B4) -#define APBDEV_PMC_IO_DPD_REQ (0x1B8) -#define APBDEV_PMC_IO_DPD_STATUS (0x1BC) -#define APBDEV_PMC_IO_DPD2_REQ (0x1C0) -#define APBDEV_PMC_IO_DPD2_STATUS (0x1C4) -#define APBDEV_PMC_SEL_DPD_TIM (0x1C8) -#define APBDEV_PMC_SCRATCH45 (0x234) -#define APBDEV_PMC_SCRATCH46 (0x238) -#define APBDEV_PMC_SCRATCH49 (0x244) -#define APBDEV_PMC_TSC_MULT (0x2B4) -#define APBDEV_PMC_STICKY_BITS (0x2C0) -#define APBDEV_PMC_WEAK_BIAS (0x2C8) -#define APBDEV_PMC_GPU_RG_CNTRL (0x2D4) -#define APBDEV_PMC_CNTRL2 (0x440) -#define APBDEV_PMC_FUSE_CTRL (0x450) -#define APBDEV_PMC_IO_DPD3_REQ (0x45C) -#define APBDEV_PMC_IO_DPD3_STATUS (0x460) -#define APBDEV_PMC_IO_DPD4_REQ (0x464) -#define APBDEV_PMC_IO_DPD4_STATUS (0x468) -#define APBDEV_PMC_SET_SW_CLAMP (0x47C) -#define APBDEV_PMC_WAKE_DEBOUNCE_EN (0x4D8) -#define APBDEV_PMC_DDR_CNTRL (0x4E4) -#define APBDEV_PMC_SEC_DISABLE (0x004) -#define APBDEV_PMC_SEC_DISABLE2 (0x2C4) -#define APBDEV_PMC_SEC_DISABLE3 (0x2D8) -#define APBDEV_PMC_SEC_DISABLE4 (0x5B0) -#define APBDEV_PMC_SEC_DISABLE5 (0x5B4) -#define APBDEV_PMC_SEC_DISABLE6 (0x5B8) -#define APBDEV_PMC_SEC_DISABLE7 (0x5BC) -#define APBDEV_PMC_SEC_DISABLE8 (0x5C0) -#define APBDEV_PMC_SCRATCH43 (0x22C) -#define APBDEV_PMC_SCRATCH190 (0x818) -#define APBDEV_PMC_SCRATCH200 (0x840) -#define APBDEV_PMC_SEC_DISABLE3 (0x2D8) -#define APBDEV_PMC_SECURE_SCRATCH4 (0x0C0) -#define APBDEV_PMC_SECURE_SCRATCH5 (0x0C4) -#define APBDEV_PMC_SECURE_SCRATCH6 (0x224) -#define APBDEV_PMC_SECURE_SCRATCH7 (0x228) -#define APBDEV_PMC_SECURE_SCRATCH16 (0x320) -#define APBDEV_PMC_SECURE_SCRATCH21 (0x334) -#define APBDEV_PMC_SECURE_SCRATCH24 (0x340) -#define APBDEV_PMC_SECURE_SCRATCH25 (0x344) -#define APBDEV_PMC_SECURE_SCRATCH26 (0x348) -#define APBDEV_PMC_SECURE_SCRATCH27 (0x34C) -#define APBDEV_PMC_SECURE_SCRATCH32 (0x360) -#define APBDEV_PMC_SECURE_SCRATCH34 (0x368) -#define APBDEV_PMC_SECURE_SCRATCH35 (0x36C) -#define APBDEV_PMC_SECURE_SCRATCH39 (0x37C) -#define APBDEV_PMC_SECURE_SCRATCH51 (0x3AC) -#define APBDEV_PMC_SECURE_SCRATCH55 (0x3BC) -#define APBDEV_PMC_SECURE_SCRATCH74 (0x408) -#define APBDEV_PMC_SECURE_SCRATCH75 (0x40C) -#define APBDEV_PMC_SECURE_SCRATCH76 (0x410) -#define APBDEV_PMC_SECURE_SCRATCH77 (0x414) -#define APBDEV_PMC_SECURE_SCRATCH78 (0x418) -#define APBDEV_PMC_SECURE_SCRATCH99 (0xAE4) -#define APBDEV_PMC_SECURE_SCRATCH100 (0xAE8) -#define APBDEV_PMC_SECURE_SCRATCH101 (0xAEC) -#define APBDEV_PMC_SECURE_SCRATCH102 (0xAF0) -#define APBDEV_PMC_SECURE_SCRATCH103 (0xAF4) -#define APBDEV_PMC_SECURE_SCRATCH112 (0xB18) -#define APBDEV_PMC_SECURE_SCRATCH113 (0xB1C) -#define APBDEV_PMC_SECURE_SCRATCH114 (0xB20) -#define APBDEV_PMC_SECURE_SCRATCH115 (0xB24) -#define APBDEV_PMC_SECURE_SCRATCH119 (0xB34) +#define APBDEV_PMC_CNTRL (0x000) +#define APBDEV_PMC_WAKE_MASK (0x00C) +#define APBDEV_PMC_WAKE_LVL (0x010) +#define APBDEV_PMC_WAKE_STATUS (0x014) +#define APBDEV_PMC_DPD_PADS_ORIDE (0x01C) +#define APBDEV_PMC_DPD_SAMPLE (0x020) +#define APBDEV_PMC_DPD_ENABLE (0x024) +#define APBDEV_PMC_CLAMP_STATUS (0x02C) +#define APBDEV_PMC_PWRGATE_TOGGLE (0x030) +#define APBDEV_PMC_REMOVE_CLAMPING_CMD (0x034) +#define APBDEV_PMC_PWRGATE_STATUS (0x038) +#define APBDEV_PMC_PWRGOOD_TIMER (0x03C) +#define APBDEV_PMC_BLINK_TIMER (0x040) +#define APBDEV_PMC_NO_IOPOWER (0x044) +#define APBDEV_PMC_PWR_DET (0x048) +#define APBDEV_PMC_SCRATCH0 (0x050) +#define APBDEV_PMC_SCRATCH1 (0x054) +#define APBDEV_PMC_SCRATCH4 (0x060) +#define APBDEV_PMC_SCRATCH12 (0x080) +#define APBDEV_PMC_SCRATCH13 (0x084) +#define APBDEV_PMC_SCRATCH18 (0x098) +#define APBDEV_PMC_SCRATCH20 (0x0A0) +#define APBDEV_PMC_AUTO_WAKE_LVL_MASK (0x0DC) +#define APBDEV_PMC_WAKE_DELAY (0x0E0) +#define APBDEV_PMC_PWR_DET_VAL (0x0E4) +#define APBDEV_PMC_CRYPTO_OP (0x0F4) +#define APBDEV_PMC_SCRATCH31 (0x118) +#define APBDEV_PMC_SCRATCH32 (0x11C) +#define APBDEV_PMC_SCRATCH33 (0x120) +#define APBDEV_PMC_SCRATCH39 (0x138) +#define APBDEV_PMC_SCRATCH40 (0x13C) +#define APBDEV_PMC_WAKE2_MASK (0x160) +#define APBDEV_PMC_WAKE2_LVL (0x164) +#define APBDEV_PMC_WAKE2_STATUS (0x168) +#define APBDEV_PMC_AUTO_WAKE2_LVL_MASK (0x170) +#define APBDEV_PMC_OSC_EDPD_OVER (0x1A4) +#define APBDEV_PMC_CLK_OUT_CNTRL (0x1A8) +#define APBDEV_PMC_RST_STATUS (0x1B4) +#define APBDEV_PMC_IO_DPD_REQ (0x1B8) +#define APBDEV_PMC_IO_DPD_STATUS (0x1BC) +#define APBDEV_PMC_IO_DPD2_REQ (0x1C0) +#define APBDEV_PMC_IO_DPD2_STATUS (0x1C4) +#define APBDEV_PMC_SEL_DPD_TIM (0x1C8) +#define APBDEV_PMC_SCRATCH45 (0x234) +#define APBDEV_PMC_SCRATCH46 (0x238) +#define APBDEV_PMC_SCRATCH49 (0x244) +#define APBDEV_PMC_TSC_MULT (0x2B4) +#define APBDEV_PMC_STICKY_BITS (0x2C0) +#define APBDEV_PMC_WEAK_BIAS (0x2C8) +#define APBDEV_PMC_GPU_RG_CNTRL (0x2D4) +#define APBDEV_PMC_CNTRL2 (0x440) +#define APBDEV_PMC_FUSE_CTRL (0x450) +#define APBDEV_PMC_IO_DPD3_REQ (0x45C) +#define APBDEV_PMC_IO_DPD3_STATUS (0x460) +#define APBDEV_PMC_IO_DPD4_REQ (0x464) +#define APBDEV_PMC_IO_DPD4_STATUS (0x468) +#define APBDEV_PMC_SET_SW_CLAMP (0x47C) +#define APBDEV_PMC_WAKE_DEBOUNCE_EN (0x4D8) +#define APBDEV_PMC_DDR_CNTRL (0x4E4) +#define APBDEV_PMC_SEC_DISABLE (0x004) +#define APBDEV_PMC_SEC_DISABLE2 (0x2C4) +#define APBDEV_PMC_SEC_DISABLE3 (0x2D8) +#define APBDEV_PMC_SEC_DISABLE4 (0x5B0) +#define APBDEV_PMC_SEC_DISABLE5 (0x5B4) +#define APBDEV_PMC_SEC_DISABLE6 (0x5B8) +#define APBDEV_PMC_SEC_DISABLE7 (0x5BC) +#define APBDEV_PMC_SEC_DISABLE8 (0x5C0) +#define APBDEV_PMC_SCRATCH43 (0x22C) +#define APBDEV_PMC_SCRATCH190 (0x818) +#define APBDEV_PMC_SCRATCH200 (0x840) +#define APBDEV_PMC_SEC_DISABLE3 (0x2D8) +#define APBDEV_PMC_SECURE_SCRATCH4 (0x0C0) +#define APBDEV_PMC_SECURE_SCRATCH5 (0x0C4) +#define APBDEV_PMC_SECURE_SCRATCH6 (0x224) +#define APBDEV_PMC_SECURE_SCRATCH7 (0x228) +#define APBDEV_PMC_SECURE_SCRATCH16 (0x320) +#define APBDEV_PMC_SECURE_SCRATCH21 (0x334) +#define APBDEV_PMC_SECURE_SCRATCH24 (0x340) +#define APBDEV_PMC_SECURE_SCRATCH25 (0x344) +#define APBDEV_PMC_SECURE_SCRATCH26 (0x348) +#define APBDEV_PMC_SECURE_SCRATCH27 (0x34C) +#define APBDEV_PMC_SECURE_SCRATCH32 (0x360) +#define APBDEV_PMC_SECURE_SCRATCH34 (0x368) +#define APBDEV_PMC_SECURE_SCRATCH35 (0x36C) +#define APBDEV_PMC_SECURE_SCRATCH39 (0x37C) +#define APBDEV_PMC_SECURE_SCRATCH51 (0x3AC) +#define APBDEV_PMC_SECURE_SCRATCH55 (0x3BC) +#define APBDEV_PMC_SECURE_SCRATCH74 (0x408) +#define APBDEV_PMC_SECURE_SCRATCH75 (0x40C) +#define APBDEV_PMC_SECURE_SCRATCH76 (0x410) +#define APBDEV_PMC_SECURE_SCRATCH77 (0x414) +#define APBDEV_PMC_SECURE_SCRATCH78 (0x418) +#define APBDEV_PMC_SECURE_SCRATCH99 (0xAE4) +#define APBDEV_PMC_SECURE_SCRATCH100 (0xAE8) +#define APBDEV_PMC_SECURE_SCRATCH101 (0xAEC) +#define APBDEV_PMC_SECURE_SCRATCH102 (0xAF0) +#define APBDEV_PMC_SECURE_SCRATCH103 (0xAF4) +#define APBDEV_PMC_SECURE_SCRATCH112 (0xB18) +#define APBDEV_PMC_SECURE_SCRATCH113 (0xB1C) +#define APBDEV_PMC_SECURE_SCRATCH114 (0xB20) +#define APBDEV_PMC_SECURE_SCRATCH115 (0xB24) +#define APBDEV_PMC_SECURE_SCRATCH119 (0xB34) + +#define APBDEV_PMC_TZRAM_PWR_CNTRL (0xBE8) +#define APBDEV_PMC_TZRAM_SEC_DISABLE (0xBEC) +#define APBDEV_PMC_TZRAM_NON_SEC_DISABLE (0xBF0) #define PMC_REG_BITS_MASK(NAME) REG_NAMED_BITS_MASK (APBDEV_PMC, NAME) @@ -247,3 +251,12 @@ DEFINE_PMC_REG_BIT_ENUM(STICKY_BITS_JTAG_STS, 6, ENABLE, DISABLE); DEFINE_PMC_REG_BIT_ENUM(CNTRL2_WAKE_DET_EN, 9, DISABLE, ENABLE); DEFINE_PMC_REG_BIT_ENUM(SEC_DISABLE2_WRITE21, 26, OFF, ON); + +DEFINE_PMC_REG(TZRAM_PWR_CNTRL_TZRAM_SD, 0, 1); +DEFINE_PMC_REG(TZRAM_PWR_CNTRL_TZRAM_SLCG_OVR, 1, 1); + +DEFINE_PMC_REG_BIT_ENUM(TZRAM_SEC_DISABLE_SD_WRITE, 0, OFF, ON); +DEFINE_PMC_REG_BIT_ENUM(TZRAM_SEC_DISABLE_SD_READ, 1, OFF, ON); + +DEFINE_PMC_REG_BIT_ENUM(TZRAM_NON_SEC_DISABLE_SD_WRITE, 0, OFF, ON); +DEFINE_PMC_REG_BIT_ENUM(TZRAM_NON_SEC_DISABLE_SD_READ, 1, OFF, ON);